1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the self-testing of memories within data processing systems to detect memory defects.
2. Description of the Prior Art
It is known to provide data processing systems incorporating memories with self-testing mechanisms, sometimes termed built-in self-test (BIST), such that when memory circuits have been fabricated, a series of self-tests can be performed to determine whether there are any memory defects present in that data processing system, which would indicate that circuits should be rejected.
As technology progresses there is a trend for memory sizes to increase in order to enable provision of more advanced applications. Accordingly, the defect density of these larger memories is becoming increasingly significant and the self-testing requirements more onerous. Furthermore, the memory modules incorporated in data processing systems vary considerably in physical configuration (i.e. the number of rows and columns comprising the memory array) and also vary in implementation such that a given address bit may select between adjacent rows in one implementation whereas it may select between adjacent columns or banks in another implementation. This presents a difficulty in provision of a generic memory self-test system, since BIST self-test algorithms target particular memory cell physical access patterns to expose particular memory defects. Failure to address memory cells according to the intended physical access patterns may result in loss of test quality, since in this case the algorithms no longer address the intended particular physical memory cells (locations) in precise sequential steps. For example a test may rely on an entire row of memory cells being set to a logical value 1, but the implementation-dependent addressing may mean that the addresses generated by the self-test instruction corresponds to a column and not a row. Thus, self-test algorithms such as a “bitline stress test” or a “checkerboard test” would not be correctly implemented if the memory cell physical access pattern did not match the intended memory cell physical access pattern due to differences in mappings between memory address indices and physical locations (i.e. cells) of a memory array.